Conventional automatic test equipment (ATE) tests semiconductor devices using the functional test approach. The goal of the functional test approach is to verify that the device performs its intended function under a variety of realistic operating conditions. Use of the functional test approach typically requires the generation of functional test patterns which exercise the device through its external interface.
However, as device complexities and densities increase, the cost of the conventional functional test approach can increase dramatically. In particular, the volume of functional test pattern data required to achieve acceptable fault coverage may increase exponentially with the size of the device. To offset these costs, many semiconductor manufacturers have looked towards structured design-for-testability (DFT) methods. With structured DFT methods the goal changes from verification of functionality to finding manufacturing defects. These methods generally rely on additional circuitry provided on the device to enhance the controllability and observability of the internal state of the device. Examples of DFT methods include scan testing, built-in-self-test (BIST), and core test (embedded microprocessor cores, etc.).
“Scan testing” is one common DFT method which has been used to test semiconductor devices and printed circuit boards for many years. With scan testing, “scan chains” (serially connected chains of storage cells) are inserted into the design. To test such a device, signals are first shifted serially into the device through the primary input pins to initialize the cells in the scan chain. Then the device is clocked for some number of cycles to propagate each scan cell's value into the adjacent combinational logic, after which the output of that logic is recaptured into the scan chain. Finally, the scan chain contents are serially shifted out of the device through its primary output pins and compared to expected values. From a test generation perspective, the effect of this approach is to make a sequential design appear like a combinational design with a larger number of pins, as scan cells behave effectively as pseudo inputs and outputs.
Nowadays, the generation of scan test patterns is performed by automatic test pattern generation (ATPG) tools. ATPG tools use knowledge of the device design and available scan chains to generate patterns which target specific faults. This is in contrast with the functional test pattern generation approach, which generally produces test patterns to exercise device behaviors and later performs a fault coverage tool check to see which faults the patterns detect.
Some ATPG tools are also capable of performing diagnosis, which is essentially the reverse of the pattern generation process. To perform diagnosis, the ATPG tool reads a list of observed scan cell failures for a given pattern and determines a gate or set of gates which would explain the failures if those gates had certain manufacturing defects.
However, to make use of these tools, the device must generally be tested using the ATPG patterns, and the failures captured on the tester must somehow be routed back to the diagnosis tool. At a minimum, this often requires pattern conversion (converting the ATPG pattern into a manufacturing tester pattern) and result conversion (converting the output of the manufacturing tester into a format readable by the diagnosis tool). Pattern conversion involves translation from the ATPG pattern format (usually STIL or WGL for scan patterns) into the proprietary test pattern format of the manufacturing tester. Result conversion involves translation from the domain of failing ATE pattern names and addresses to the domain of failing scan cells relative to ATPG pattern names. Therefore, result translation generally requires some knowledge of how the ATPG patterns were translated into manufacturing test patterns, thus complicating the process.
Once results are converted into the appropriate form for the diagnosis tool, the diagnosis tool can be invoked to perform diagnosis on the scan failures, producing logical defect data. From this point on, other available tools may be used to translate the logical defect data into the physical locations of the defects, and then to analyze the physical failures at these locations to determine the underlying causes and possible remedies.
For example, Maier and Smith describe an improved diagnostic process in their article entitled “A New Diagnostic Methodology.” Their process first involves translation of logical diagnosis results such as produced by the process described here into physical locations which can then be combined with in-line electrical test data such as that produced by optical inspection equipment. By correlating test failures to physical defects, they allegedly reduce the number of hardware samples submitted to failure analysis technicians. This allegedly reduces the normally long turnaround time it takes to get feedback from diagnostic data. The specific mapping tools described include a wafermap tool which overlays electrical test data with optical inspection data. Additionally, a per-die layout-oriented mapping tool is provided to support the accumulation of multiple data sets to identify “hot spots” in the device design.
While the conventional techniques described above are beneficial for their intended purposes, the lack of automation between the ATE and the diagnosis tool is problematic. Existing pattern conversion tools are not integrated with the result translation process, so existing result translation solutions generally embed knowledge about the particular ATPG/diagnosis tool, pattern conversion tool, ATE, test program, andlor device and must therefore be modified when any of these changes. Moreover, the failure data identified and processed is typically not readily user-comprehensible. The DFT result diagnosis system and method of the present invention addresses these problems.